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IEICE Transactions on Information and Systems 2007 E90-D(3):637-647; doi:10.1093/ietisy/e90-d.3.637
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Copyright © 2007 The Institute of Electronics, Information and Communication Engineers

Regular Section -- Papers -- VLSI Systems

Dynamic Reconfiguration of Cache Indexing in Embedded Processors

Junhee KIM1, Sung-Soo LIM2 and Jihong KIM1

1 The authors are with the School of Computer Science and Engineering, Seoul National University, Seoul, 151–742 Korea. E-mail: jihong{at}davinci.snu.ac.kr, 2 The author is with the School of Computer Science, Kookmin University, Seoul, 151–742 Korea.


  Abstract

Cache performance optimization is an important design consideration in building high-performance embedded processors. Unlike general-purpose microprocessors, embedded processors can take advantages of application-specific information in optimizing the cache performance. One of such examples is to use modified cache index bits (over conventional index bits) based on memory access traces from key target embedded applications so that the number of conflict misses can be reduced. In this paper, we present a novel fine-grained cache reconfiguration technique which allows an intra-program reconfiguration of cache index bits, thus better reflecting the changing characteristics of a program execution. The proposed technique, called dynamic reconfiguration of index bits (DRIB), dynamically changes cache index bits in the function level. This compiler-directed and fine-grained approach allows each function to be executed using its own optimal index bits with no additional hardware support. In order to avoid potential performance degradation by frequent cache invalidations from reconfiguring cache index bits, we describe an efficient algorithm for selecting target functions whose cache index bits are reconfigured. Our algorithm ensures that the number of cache misses reduced by DRIB outnumbers the number of cache misses increased from cache invalidations. We also propose a new cache architecture, Two-Level Indexing (TLI) cache, which further reduces the number of conflict misses by intelligently dividing indexing steps into two stages. Our experimental results show that the DRIP approach combined with the TLI cache reduces the number of cache misses by 35% over the conventional cache indexing technique.

Key Words: cache indexing, cache organization, dynamic reconfiguration, embedded processor, microprocessor architecture

Manuscript received December 28, 2005. Manuscript revised July 2, 2006.


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