Copyright © 2007 The Institute of Electronics, Information and Communication Engineers
Regular Section -- Letters -- VLSI Systems |
Latency-Aware Bus Arbitration for Real-Time Embedded Systems
1 The authors are with Yonsei University, Seoul, Korea., 2 The author is with Cisco Systems Incorporation, CA, USA., 3 Corresponding author. E-mail: eychung{at}yonsei.ac.kr
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Abstract |
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We present a latency-aware bus arbitration scheme for real-time embedded systems. Only a few works have addressed the quality of service (QoS) issue for traditional busses or interconnection network. They mostly aimed at minimizing the latencies of several master blocks, resulting in decreasing overall bandwidth and/or increasing the latencies of other master blocks. In our method, the optimization goal is different in that the latency of a master should be as close as a given latency constraint. This is achieved by introducing the concept of "slack". In this method, masters effectively share the given communication architecture so that they all observe expected latencies and the degradation of overall bandwidth is marginal. The experimental results show that our method greatly reduces the number of constraint violations compared to other conventional arbitration schemes while minimizing the bandwidth degradation.
Key Words: latency, arbiter, QoS, performance, bus, slack
Manuscript received July 11, 2006. Manuscript revised September 13, 2006.