Copyright © 2008 The Institute of Electronics, Information and Communication Engineers
Regular Section -- Letters -- Dependable Computing |
MTR-Fill: A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs
1 The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Korea. E-mail: songdongsup{at}dopey.yonsei.ac.kr, E-mail: shkang{at}yonsei.ac.kr, 2 The author is with the Department of Electronic Engineering, Hoseo University, Korea.
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Abstract |
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This paper proposes the minimum transition random X-filling (MTR-fill) technique, which is a new X-filling method, to reduce the amount of power dissipation during scan-based testing. In order to model the amount of power dissipated during scan load/unload cycles, the total weighted transition metric (TWTM) is introduced, which is calculated by the sum of the weighted transitions in a scan-load of a test pattern and a scan-unload of a test response. The proposed MTR-fill is implemented by simulated annealing method. During the annealing process, the TWTM of a pair of test patterns and test responses are minimized. Simultaneously, the MTR-fill attempts to increase the randomness of test patterns in order to reduce the number of test patterns needed to achieve adequate fault coverage. The effectiveness of the proposed technique is shown through experiments for ISCAS'89 benchmark circuits.
Key Words: low power test, scan-based test, X-filling, test application time
Manuscript received September 5, 2007. Manuscript revised November 30, 2007.