Copyright © 2007 The Institute of Electronics, Information and Communication Engineers
Regular Section -- Papers -- Computer Components |
Adaptive Error Compensation for Low Error Fixed-Width Squarers*
1 The authors are with the Dept. of Electronics & Information Engr., Chonbuk National University, Jeonju, Korea. E-mail: kjcho{at}chonbuk.ac.kr, jgchung{at}chonbuk.ac.kr
In this paper, we present a design method for fixed-width squarer that receives an n-bit input and produces an n-bit squared product. To efficiently compensate for the truncation error, modified Booth-folding encoder signals are used for the generation of error compensation bias. The truncated bits are divided into two groups (major and minor) depending upon their effects on the truncation error. Then, different error compensation methods are applied to each group. By simulations, it is shown that the proposed fixed-width squarers have lower error than other fixed-width squarers and are cost-effective.
Key Words: fixed-width, squarer, Booth-folding, truncation error, error compensation
Manuscript received February 22, 2006. Manuscript revised September 5, 2006.
* This research was supported by the MIC (Ministry of Information and Communication), Korea, under the ITRC (Information Technology Research Center) support program supervised by the IITA (Institute of Information Technology Assessment) (IITA-2006-C1090-0603-0024).
References
[1] K.E. Wires, M.J. Schulte, L.P. Marquette, and P.I. Balzola, "Combined unsigned and two's complement squarers," Proc. 34th Asilomar conference on Signals, Systems, and Computers, pp.1215–1219, Pacific Grove, CA, 1999.
[2] J. Pihl and E.J. Aas, "A multiplier and squarer generator for high performance DSP applications," Proc. IEEE 39th Midwest Symp. on Circuits and Systems, pp.109–112, Aug. 1996.
[3] J.T. Yoo, K.F. Smith, and G. Gopalakrishnan, "A fast parallel squarer based on divide-and-conquer," IEEE J. Solid-State Circuits, vol.32, no.6, pp.909–912, June 1997.
[4] R.K. Kolagotla, W.R. Griescbach, and H.R. Srinivas, "VLSI implementation of a 350 MHz 0.35 µm 8 bit merged squarer," Electron. Lett., vol.34, no.1, pp.47–48, Jan. 1998.
[5] D.D. Caro and A.G.M. Strollo, "Parallel squarer using Booth-folding technique," Electron. Lett., vol.37, no.6, pp.346–347, March 2001.
[6] S.S. Kidambi, F. El-Guibaly, and A. Antoniou, "Area-efficient multipliers for digital signal processing applications," IEEE Trans. Circuits Syst. II, vol.43, no.2, pp.90–94, Feb. 1996.
[7] L.D. Van and C.C. Yang, "Generalized low-error area-efficient fixed-width multipliers," IEEE Trans. Circuits Syst. II, vol.52, no.8, pp.1608–1619, Aug. 2005.
[8] S.J. Jou, M.H. Tsai, and Y.L. Tsao, "Low-error reduced-width Booth multipliers for DSP applications," IEEE Trans. Circuits Syst. I, vol.50, no.11, pp.1470–1474, Nov. 2003.
[9] K.J. Cho, K.C. Lee, J.G. Chung, and K.K. Parhi, "Design of low error fixed-width modified Booth multiplier," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.12, no.5, pp.522–531, May 2004.
[10] K.J. Cho, E.M. Choi, J.G. Chung, M.S. Lim, and J.W. Kim, "Low error fixed-width squarer design," Proc. 2003 IEEE ISCAS, pp.137–140, Bangkok, Thailand, May 2003.
[11] E.G. Walters, M.J. Schulte, and M.G. Arnold, "Truncated squarers with constant and variable correction," Proc. SPIE: Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, pp.40–50, Denver, CO, Oct. 2004.
[12] O.L. MacSorley, "High speed arithmetic in binary computers," Proc. IRE, vol.49, pp.67–91, Jan. 1961.
CiteULike 
Connotea 
Del.icio.us What's this?
| ||||||||||||||||||||||||||||||||||||||||||||||||||