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IEICE Transactions on Information and Systems 2007 E90-D(3):676-679; doi:10.1093/ietisy/e90-d.3.676
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Copyright © 2007 The Institute of Electronics, Information and Communication Engineers

Regular Section -- Letters -- VLSI Systems

Latency-Aware Bus Arbitration for Real-Time Embedded Systems

Minje JUN1, Kwanhu BANG1, Hyuk-Jun LEE2 and Eui-Young CHUNG1,3

1 The authors are with Yonsei University, Seoul, Korea., 2 The author is with Cisco Systems Incorporation, CA, USA., 3 Corresponding author. E-mail: eychung{at}yonsei.ac.kr

We present a latency-aware bus arbitration scheme for real-time embedded systems. Only a few works have addressed the quality of service (QoS) issue for traditional busses or interconnection network. They mostly aimed at minimizing the latencies of several master blocks, resulting in decreasing overall bandwidth and/or increasing the latencies of other master blocks. In our method, the optimization goal is different in that the latency of a master should be as close as a given latency constraint. This is achieved by introducing the concept of "slack". In this method, masters effectively share the given communication architecture so that they all observe expected latencies and the degradation of overall bandwidth is marginal. The experimental results show that our method greatly reduces the number of constraint violations compared to other conventional arbitration schemes while minimizing the bandwidth degradation.

Key Words: latency, arbiter, QoS, performance, bus, slack


Manuscript received July 11, 2006. Manuscript revised September 13, 2006.

References

[1] A. Sangiovanni-Vincentelli, L. Carloni, F.D. Bernardinis, and M. Sgroi, "Benefits and challenges for platform-based design," DAC, pp.409–414, 2004.

[2] U.Y. Ogras, J. Hu, and R. Marculescu, "Communication-centric SoC design for nanoscale domain," ASAP 2005, pp.73–78, 2005.

[3] K. Lahiri, A. Raghunathan, and G. Lakshminarayana, "LOTTERYBUS: A new high performance communication architecture for system on chip designs," DAC, pp.15–20, 2001.

[4] W.D. Weber, J. Chou, J. Swarbrick, and D. Wingard, "A quality of service mechanism for interconnection networks in system on chips," DATE, pp.1232–1237, 2005.

[5] R. Lu and C. Koh, "SAMBA-BUS: A high performance bus architecture for system on chips," ICCAD, 2003.

[6] K. Sekar, K. Lahiri, A. Raghunathan, and S. Dey, "FLEXBUS: A high performance system-on-chip communication architecture with a dynamically configurable topology," DAC, pp.571–574, 2005.

[7] A. Radulescu, J. Dielissen, K. Goossens, E. Rijpkema, and P. Wielage, "An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration," DATE, vol.2, pp.878–883.

[8] K. Kim, S. Lee, K. Lee, and H. Yoo, "An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip," IEEE Circuits and Systems, pp.2357–2360, 2005.

[9] ARM, Limited. AMBA Specification, 1999.


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This Article
Right arrow Abstract Freely available
Right arrow Full Text (PDF)
Right arrow Alert me when this article is cited
Right arrow Alert me if a correction is posted
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Right arrow Articles by JUN, M.
Right arrow Articles by CHUNG, E.-Y.
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 Add to CiteULike   Add to Connotea   Add to Del.icio.us  
What's this?