IEICE Transactions on Information and Systems

IEICE Transactions on Information and Systems 2007 E90-D(3):685-687; doi:10.1093/ietisy/e90-d.3.685

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Copyright © 2007 The Institute of Electronics, Information and Communication Engineers

Regular Section -- Letters -- Dependable Computing

Detection of CMOS Open Node Defects by Frequency Analysis

Hiroyuki MICHINISHI¹, Tokumi YOKOHIRA², Takuji OKAMOTO¹, Toshifumi KOBAYASHI³ and Tsutomu HONDO⁴

¹ The authors are with the Faculty of Engineering, Okayama University of Science, Okayama-shi, 700–0005 Japan. E-mail: mitinisi{at}ee.ous.ac.jp, ² The author is with the Faculty of Engineering, Okayama University, Okayama-shi, 700–8530 Japan., ³ The author is with SOC Division, Renesas Technology Corporation, Itami-shi, 664–8641 Japan., ⁴ The author is with Sharp Takaya Electronics Industry Co., Ltd., Okayama-ken, 719–0301 Japan.

A method to detect open node defects that cannot be detected by the conventional IDDQ test method has previously been proposed employing a sinusoidal wave superposed on the DC supply voltage. The present paper proposes a strategy to improve the detectability of the test method by means of frequency analysis of the supply current. In this strategy, defects are detected by determining whether secondary harmonics of the sinusoidal wave exist in the supply current. The effectiveness of the method is confirmed by experiments on two CMOS NAND gate packages (SSIs).

Key Words: current test, open node defect, floating gate defect, frequency analysis

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Manuscript received September 8, 2006.

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This Article Abstract Full Text (PDF) Alert me when this article is cited Alert me if a correction is posted Services Email this article to a friend Similar articles in this journal Alert me to new issues of the journal Add to My Personal Archive Download to citation manager Request Permissions Google Scholar Articles by MICHINISHI, H. Articles by HONDO, T. Search for Related Content Social Bookmarking          What's this?