IEICE Transactions on Information and Systems

IEICE Transactions on Information and Systems 2008 E91-D(4):1197-1200; doi:10.1093/ietisy/e91-d.4.1197

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Copyright © 2008 The Institute of Electronics, Information and Communication Engineers

Regular Section -- Letters -- Dependable Computing

MTR-Fill: A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs

Dong-Sup SONG¹, Jin-Ho AHN², Tae-Jin KIM¹ and Sungho KANG¹

¹ The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Korea. E-mail: songdongsup{at}dopey.yonsei.ac.kr, E-mail: shkang{at}yonsei.ac.kr, ² The author is with the Department of Electronic Engineering, Hoseo University, Korea.

This paper proposes the minimum transition random X-filling (MTR-fill) technique, which is a new X-filling method, to reduce the amount of power dissipation during scan-based testing. In order to model the amount of power dissipated during scan load/unload cycles, the total weighted transition metric (TWTM) is introduced, which is calculated by the sum of the weighted transitions in a scan-load of a test pattern and a scan-unload of a test response. The proposed MTR-fill is implemented by simulated annealing method. During the annealing process, the TWTM of a pair of test patterns and test responses are minimized. Simultaneously, the MTR-fill attempts to increase the randomness of test patterns in order to reduce the number of test patterns needed to achieve adequate fault coverage. The effectiveness of the proposed technique is shown through experiments for ISCAS'89 benchmark circuits.

Key Words: low power test, scan-based test, X-filling, test application time

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Manuscript received September 5, 2007. Manuscript revised November 30, 2007.

Reference

[1] T. Hayashi, N. Ikeda, T. Shinogi, H. Takase, and H. Kita, "Low power oriented test modification and compression techniques for scan based core testing," IEEE Proc. Asian Test Symposium, pp.327–332, 2006.

[2] N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, and H.J. Wonderlich, "Minimizing peak power consumption during scan testing: Structural technique for don't care bits assignment," IEEE Proc. Research in Microelectronics and Electronics, Ph. D., pp.65–68, 2006.

[3] J. Song, H. Yi, D. Hwang, and S. Park, "A compression improvement technique for low-power scan test data," IEEE Proc. TENCON, pp.1–4, 2006.

[4] K.M. Butler, J. Saxena, T. Fryars, G. Hetheringon, A. Jain, and J. Lewis, "Minimizing power consumption in scan testing: Pattern generation and DFT techniques," IEEE Proc. Int. Test Conf., pp.355–364, 2004.

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This Article Abstract Full Text (PDF) Alert me when this article is cited Alert me if a correction is posted Services Email this article to a friend Similar articles in this journal Alert me to new issues of the journal Add to My Personal Archive Download to citation manager Request Permissions Google Scholar Articles by SONG, D.-S. Articles by KANG, S. Social Bookmarking          What's this?