Copyright © 2006 The Institute of Electronics, Information and Communication Engineers
Regular Section -- Letters -- VLSI Systems |
Design and Evaluation of Data-Dependent Hardware for AES Encryption Algorithm*
1 The authors are with the Department of Knowledge-based Information Engineering, Toyohashi University of Technology, Toyohashi-shi, 441–8580 Japan., 2 The author is with the Intelligent Sensing System Research Center, Toyohashi University of Technology, Toyohashi-shi, 441–8580 Japan. E-mail: ichikawa{at}tutkie.tut.ac.jp, 3 Presently, with HAL Laboratory, Inc.
If a logic circuit was specialized to a specific input, the derived circuit would be faster and smaller than the original. This study presents various designs of a key-specific AES encryption circuit. In our iterative design, 41% of the logic gates and 20% of RAM were reduced, while 24% more performance was derived. In our pipelined design, 54% of the logic gates and 20% of RAM were reduced, while 74% higher performance was achieved. The results on DES encryption circuits are also presented for comparison.
Key Words: FPGA, custom circuit, partial evaluation, specialization, cryptography, embedded system
Manuscript received August 30, 2005. Manuscript revised March 27, 2006.
* This work partially appeared as an extended abstract in the 2005 Annual Meeting Record IEE Japan, vol.3, pp.91–92 (March 2005).